1. Technical Field
The present invention relates to semiconductor devices, and more particularly to devices with a gate structure with reduced gate resistance and methods for fabricating the same.
2. Description of the Related Art
Conventional top-gated field effect transistors (FET) include a number of associated parasitics. With continuous gate-length scaling associated with denser device layouts, FET gate resistance increases. As a result, maximum oscillating frequency (fMAX) performance of complementary metal oxide semiconductor (CMOS) FETs has improved little beyond the 45 nm node. With conventional CMOS fabrication techniques, gate resistance can only be reduced by using multiple fingers, decreasing device width or employing a double-contacted gate structure. In such devices, additional metal layers (with lower resistance than poly-silicon) can make contact with a gate node only outside of the device area to reduce parasitic capacitances to make the device operable.
Top-gated devices may include a mushroom gate structure having an upper portion that extends over adjacent active regions. The mushroom-like gate structure attempts to reduce gate resistance by adding material to the gate electrode, but may in some instances contribute to capacitance parasitics with surrounding metal structures.